## About adder

**Adder**plays an important role in digital devices. The addition process of the digital circuits is performed by an

**adder**.

By using adder all the mathematical procedures of computers are done. In much computational processing, adders are used in the ALU(Arithmetic Logic Unit ).

Know what are the subtractors in Digital Electronics.

Adders are mainly two types. They are,

For two single bits here we will get a sum and a carry as output for each input combination.

Adders are mainly two types. They are,

- Half Adder
- Full Adder

### 01. Half Adder:

It adds two binary bits. It has no carry addition ability that's why it is called half adder.### 02. Full Adder:

It has the ability to add two bits and also it can add carry. That's why it is called a full adder.

For two single bits here we will get a sum and a carry as output for each input combination.

A | B | Sum | Carry |

0 | 0 | 0 | 0 |

0 | 1 | 1 | 0 |

1 | 0 | 1 | 0 |

1 | 1 | 0 | 1 |

**A truth table for half adder**

In this circuit, there is a system that can add two bits and also two carries. It is called the Full adder. Let, 3 input sign of a full adder is A, B, Ci(Ci is the carry input) and two outputs are S(Addition) and Co(Carry output).

Here is a

We have to use two half adders and also we need an extra OR gate for adding the carries for designing a full adder using a half adder.

Let, the input signal for full adder is X and Y, carry Cᵢ and outputs are S (Addition) Co(Carry).

The addition of the second half adder(S₂) will be the full adder addition. By adding the carries of the first half adder(C₁) and second half adder(C₂) we will get the carry of a full adder.

Here is a

**truth table**for a full adder circuit.Input | Output | |||

A | B | Ci | S | Co |

0 | 0 | 0 | 0 | 0 |

0 | 0 | 1 | 1 | 0 |

0 | 1 | 0 | 1 | 0 |

0 | 1 | 1 | 0 | 1 |

1 | 0 | 0 | 1 | 0 |

1 | 0 | 1 | 0 | 1 |

1 | 1 | 0 | 0 | 1 |

1 | 1 | 1 | 1 | 1 |

**Output equation**

S = ĀB̄Cᵢ +ĀBC̄ᵢ + AB̄C̄ᵢ+ABCᵢ

C₀ = ĀBCᵢ+AB̄Cᵢ+ABC̄ᵢ+ABC

We can modify the addition of a full adder like this

And also the equation of output carry can be modified like this -

From modified equations of the addition of full adder (S) and carry output (Cₒ) the circuit diagram using X-OR gate will be like this-

**Full adder representation by using the basic logical gates**

A full adder can be represented by using the basic logic gates only. The circuit diagram is given below-

The full adder reduces the complexity of a logical circuit.

**Full adder using half adder**

We have to use two half adders and also we need an extra OR gate for adding the carries for designing a full adder using a half adder.

Let, the input signal for full adder is X and Y, carry Cᵢ and outputs are S (Addition) Co(Carry).

The addition of the second half adder(S₂) will be the full adder addition. By adding the carries of the first half adder(C₁) and second half adder(C₂) we will get the carry of a full adder.

In the figure, if we see for the first half adder-

Sum,

S₁ = X⊕Y ----(1)

Carry

C₁ = XY------(2)

For the second half adder-

Sum,

S₂ = S₁⊕Cᵢ

= X⊕Y⊕Cᵢ [From (1)]

= S

This the addition of a full adder.

Now,

C₂ = S₁Cᵢ = (X⊕Y)Cᵢ-----(3)

Now total carry(C₀) will be the addition of first half adder carry(C₁) and second half adder carry(C₂)

So,

C₀ = C₁+C₂ = XY+(X⊕Y)Cᵢ [From (2) and (3) ]

This is the full adder carry.

From here we get,

Sum of full adder output, S = X⊕Y⊕Cᵢ

Sum,

S₁ = X⊕Y ----(1)

Carry

C₁ = XY------(2)

For the second half adder-

Sum,

S₂ = S₁⊕Cᵢ

= X⊕Y⊕Cᵢ [From (1)]

= S

This the addition of a full adder.

Now,

C₂ = S₁Cᵢ = (X⊕Y)Cᵢ-----(3)

Now total carry(C₀) will be the addition of first half adder carry(C₁) and second half adder carry(C₂)

So,

C₀ = C₁+C₂ = XY+(X⊕Y)Cᵢ [From (2) and (3) ]

This is the full adder carry.

From here we get,

Sum of full adder output, S = X⊕Y⊕Cᵢ

Total carry of the full adder, C₀ = XY+(X⊕Y)Cᵢ

So, considering all S = 1 we get,

### Half adder to full adder using equations

Let the 3 input signals of full adder are X, Y, Cᵢ ( Cᵢ is the carry input) and outputs are S(Sum) Cₒ (Carry output). The truth table for the full adder is given below.

Input | Output | |||

X | Y | Cᵢ | S | Cₒ |

0 | 0 | 0 | 0 | 0 |

0 | 0 | 1 | 1 | 0 |

0 | 1 | 0 | 1 | 0 |

0 | 1 | 1 | 0 | 1 |

1 | 0 | 0 | 1 | 0 |

1 | 0 | 1 | 0 | 1 |

1 | 1 | 0 | 0 | 1 |

1 | 1 | 1 | 1 | 1 |

So, considering all S = 1 we get,

Again for all Cₒ = 1, we get,

Here is the diagram of the half adder to the full adder circuit.

### Ripple carry adder

The signal Cₙ₋₁ is valid after a delay of (n-1)✕dt. It is meaning that the complete sum is available after a delay of n✕dt. Because of the way they carry signals ripple through the full adder stages, the circuit in the figure is called a ripple carry adder.

Figure: An n-bit ripple carry adder

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